The inventive concepts relate to a three-dimensional (3D) semiconductor memory device and, more particularly, to a 3D semiconductor memory device with improved reliability.
Semiconductor devices have been highly integrated to satisfy consumer demands for improved performances and/or lower manufacturing costs. For example, to reduce a bit cost (e.g., manufacturing cost per bit) of semiconductor devices, semiconductor devices are desired to have increased densities. In conventional two-dimensional (2D) or planar semiconductor memory devices, integration densities of the semiconductor devices are primarily determined by an area occupied by a unit memory cell. In other words, the integration densities of the 2D or planar semiconductor memory devices are generally limited by a level of a patterning process (e.g., a resolution of a patterning process). In order to from fine patterns, extremely expensive apparatuses are generally used and this may set practical limitations on increasing integration densities for 2D or planar semiconductor memory devices. Thus, three-dimensional (3D) semiconductor memory devices having three-dimensionally arranged memory cells have been developed.